Previously we examined a binary counter that progresses through all of its possible states. Recall that the maximum number of possible states (maximum modulus) of a counter is 2n, where n is the number of flip-flops in the counter.
Counters can be designed to have a number of states in their sequence that is less than 2n. The resulting sequence is called a truncated sequence. One common modulus for counters with truncated sequences is ten. Such counters are referred to as decade counters. Furthermore, a counter with count a sequence of zero (0000) through nine (10001) is referred to as a BCD decade counter because its ten state sequence is the BCD code.
To obtain a truncated sequence it is necessary to force the counter to cycle before going through all of its normal states. For example, the BCD decade counter must recycle back to the state 0000 after state 1001. Note that a decade counter will require 4 flip-flops (three flip-flops are insufficient because 23=8).
One method that can be used to achieve recycling after the count of nine (1001) is to decode ten (1010) with a NAND gate and connect the output of the NAND gate to the clear inputs of all the flip-flops as illustrated in Figure 3(a).
Notice that only Q1 and Q3 are connected to the NAND gate inputs. This arrangement is an example of partial decoding, in which two unique states (Q1=1 and Q3=1) are enough to decode the count of 10. This is because none of the other states (zero through nine) have Q1 and Q3 high at the same time. Consequently, when the counter goes into count ten (1010) the decoding gate output goes LOW and asynchronously RESETS all of the flip-flips. The waveform (\timing) diagram of the counter is shown in Figure 3(b).
Figure 3(a): An asynchronously clocked counter
Figure 3(b): The waveform diagram of the counter is shown in Fig 3(a)
Copyright © Adrian Als , 1999
This page was last modified: Wednesday, April 12, 2000
