First, recall that a binary variable may be
either in its true form (A) or its complement (
).
Second, recall that for n variables, the maximum number of input variable
combinations is given by N = 2n. Then considering the AND gate,
each of the N logic expressions formed is called a standard product or minterm.
As indicated in Table 1-13, binary digits ‘1’ and ‘0’ are taken to
represent a given variable (e.g. A) and its complemented (e.g. ), respectively. Also from Table 1-13 note that each minterm is
assigned a symbol (Pj) each where j is the decimal equivalent to the binary
number of the minterm designated.
Similarly, if we consider an OR gate, each of the
N logic expressions formed is called a standard sum or maxterm. In
this case binary digits ‘1’ and ‘0’ are taken to represent a given
complemented variable (e.g. ) and its true form (e.g. A),
respectively. As shown in Table 1-13, a symbol (Sj) is assigned to each maxterm
where j is the decimal equivalent to the binary number of the maxterm designated. Also
observe that each maxterm is the complement of its corresponding minterm, and vice versa.
 | The complement of each term may be determined using DeMorgan’s Theorem |
Input |
Minterms |
Maxterms |
|||||
A |
B |
C |
Terms |
Designation |
Terms |
Designation |
|
0 |
0 |
0 |
|
P0 |
|
S0 |
|
0 |
0 |
1 |
|
P1 |
|
S1 |
|
0 |
1 |
0 |
|
P2 |
|
S2 |
|
0 |
1 |
1 |
|
P3 |
|
S3 |
|
1 |
0 |
0 |
|
P4 |
|
S4 |
|
1 |
0 |
1 |
|
P5 |
|
S5 |
|
1 |
1 |
0 |
|
P6 |
|
S6 |
|
1 |
1 |
1 |
|
P7 |
|
S7 |
|
Table 1-13 Minterms and Maxterms for Three Binary Variables
In short, minterms and maxterms may be used to define the two standard forms for logic expressions, namely the sum of products (SOP), or sum of minterms, and the product of sums (POS), or product of maxterms. These standard forms of expression aid the logic circuit designer by simplifying the derivation of the function to be implemented.
The SOP expression is the equation of the logic function as read off the truth table to specify the input combinations when the output is a logical 1. To illustrate, let us consider Table 1-14. Observe that the output is high for the rows labelled 3, 5 and 6. The SOP expression for this circuit is thus given any of the following:
1 2 X = P3 + P5 + P6 or 3
Row |
Input |
Output |
||
Number |
A |
B |
C |
X |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
2 |
0 |
1 |
0 |
0 |
3 |
0 |
1 |
1 |
1 |
4 |
1 |
0 |
0 |
0 |
5 |
1 |
0 |
1 |
1 |
6 |
1 |
1 |
0 |
1 |
7 |
1 |
1 |
1 |
0 |
Table 1-14 Truth Table of
The POS expression is the equation of the logic function as read off the truth table to specify the input combinations when the output is a logical 0. To illustrate, let us again consider Table 1-14. Observe that the output is low for the rows labelled 0, 1, 2, 4 and 7. The POS expression for this circuit is thus given by any of the following:
1 2 X = S0S1S2S4S7 3
Note:
Boolean functions expressed as a sum of products or a product of sums are said to be in canonical form.
Note the POS is not the complement of the SOP expression.
Derive the SOP and POS expressions for the truth tables shown below:
SOP:
Row Number
Input Output A
B
X 0
0
0
1 1
0
1
0 2
1
0
1 3
1
1
0 Table 1.15 Truth Table describing the output X
X = P0 + P2 or
POS:
X = S1S3 or
Copyright © Adrian Als , 1999
This page was last modified: Wednesday, April 12, 2000
