An important application of flip-flops is in the design digital counters. These devices generate binary numbers in a specified count sequence when triggered by an incoming clock waveform. On each trigger, the counter advances to the next number in the sequence. After reaching the final state in the sequence, the counter then recycles. Counters may be used to count up or down, to cycle through memory addresses in microprocessors applications, to generate waveforms of particular patterns and frequencies, and to activate other logic circuits in a complex process.
Counter Classification
Counters are classified according to their operational characteristics. Some of these characteristics include:
 | Count modulus (MOD) – total number of states in the counter sequence |
| Counter triggering technique – positive edge or negative edge |
| Frequency division characteristics |
| Asynchronous – no common clock – OR Synchronous - common clock - operation |
A circuit analysis is used to determine/define the operation of counter. To provide a comprehensive analysis it is important to specify the seven (7) characteristics listed below.
Asynchronous counters do not have a common clock that controls all the flip-flop stages. The control clock is input to the first stage, or the LSB stage of the counter. The clock for each stage subsequent is obtained from the flip-flop from the prior stage.
Let us analyse the 2-bit counter shown in Figure 3-15 and its corresponding waveform diagram in Figure 3-16. Note that we assume that Q0 and Q1 are LOW initially.
Figure 3-15 A two-bit asynchronous counter
Figure 3-16 Waveform Diagram for counter in Figure 3-15
| The counter has two flip-flops and two output bits, therefore it a two-stage counter. |
| The input clock does not trigger both flip-flops, therefore it is an asynchronous counter |
| The J and K inputs are tied together as kept HIGH, so they are considered to be toggle flip-flips |
| The flip-flops are positive edge triggered |
| The waveform analysis reveals that Q0 is the LSB and that its frequency is ½ the input clock frequency. Furthermore, Q1 is the MSB and that its frequency is ¼ the input clock frequency |
| The count sequence is 00,01,10,11 where the LSB is Q0. Thus it is a MOD-4 binary up counter |
The state transition diagram for this MOD-4 binary up counter is shown in figure 3-17.
Asynchronous counters are also know as ripple counters because the effect of the input clock pulse which is first "felt" by the flip-flip at the first stage cannot immediately be "felt" by the flip-flip at the second stage. This is due to the propagation delay. Thus, the effect of the input clock "ripples" through the counter until it reaches the final stage. In some texts the waveform diagram is also referred to as a timing diagram
| Specify the operational requirements – number of stages, modulus, trigger and characteristics. |
| Graph the desired output waveforms. |
| Determine the necessary output to use as the clock input to the following stager. Either the true or complemented out put could serve as the clocking signal. |
| Verify the circuit through analysis and testing. |
Copyright © Adrian Als , 1999
This page was last modified: Wednesday, April 12, 2000
