Synchronous digital counters have a common clock which results in all the flip-flops being triggered simultaneously. Consequently, there are no cumulative delays that result because the clock signal must ripple through the stages as in the asynchronous counters. Synchronous counters can be designed to count up and down in numerical order. In addition, they may be used to produce count sequences of non-consecutive numbers. The count sequence produced by synchronous counters is not dependent on the trigger characteristics of the flip-flops that comprise the count stages. The count sequence is achieved by applying the required logic function into the flip-flops.
To define the counter operation of synchronous counters we may employ a procedure similar to that used in the analysis of asynchronous counters. In particular, the following steps are used to analyse synchronous counters.
Verify that the counter is indeed synchronous (i.e. identify the common clock feature).
Determine the number of stages by counting the number of flip-flops or outputs.
Determine the type of flip-flops and the input function for each stage. For reference, recall the characteristic table which indicates the present state (Qt), the present inputs and the next state (Qt+1) for each flip flop.
Construct a characteristic table for the complete counter circuit.
Analyse the counter using the characteristic table to determine the complete counter sequence. This analysis concludes when the count sequence begins to repeat.
Determine the modulus of the counter.
Construct a state transition diagram to describe the counter operation.
Graph the output waveforms produced by the counter.
Let us now analyse the counter circuit shown in Figure 3-18.
Figure 3-18 A two-bit synchronous counter
 | The circuit is synchronous as the flip-flops are all tied to a common clocks |
| The counter has two stages |
| T flip-flops are used in the design of the counter |
J-K Flip-Flop Characteristic Table |
|||
Present Inputs J K |
Present State Qt |
Next State Qt+1 |
|
0 0 |
0 0 |
0 1 |
0 1 |
0 0 |
1 1 |
0 1 |
0 0 |
1 1 |
0 0 |
0 1 |
1 1 |
1 1 |
1 1 |
0 1 |
1 0 |
Using the flip-flip characteristic table we may now develop the counter characteristic table. Let Ji and Ki represent the inputs to the (I+1) th stage flip-flop, where i=0, 1 in this case.
Counter Characteristic Table |
|||||||||||
Present State Q1 Q0 |
Present Inputs J1 K1 J0 K0 |
Next State Q1 Q0 |
|||||||||
0 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
||||
0 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
||||
1 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
||||
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
||||
|
|||||||||||
From the analysis of the counter next state table we conclude that it is a MOD-4 binary up counter.
The state diagram is as illustrated in Figure 3-19 and the corresponding waveform diagram is chow in Figure 3-20.
Figure 3-19 State transition diagram
Figure 3-20 Waveform Diagram for counter in Figure 3-18
To successfully design synchronous counters we may employ the following six basic steps:
Create the state transition diagram.
Create a present state-next state table (often referred to as the next state table).
Expand the table to form the transition table for each flip-flop in the circuit. The transition table shows the flip-flop inputs required to make the counter go from present state to the desired next state. This is also referred to as the excitation table.
Determine the logic functions of the J and K inputs as a function of the present states.
Analyse the counter to verify the design.
Construct and test the counter.
Let us employ these techniques to design a MOD-8 counter to count in the following sequence: 0, 1, 2, 3, 4, 5, 6, 7.
Step1: Creating state transition diagram.
Step 2: Creating present state-next state table
Present State |
Next State |
||||
Q2 |
Q1 |
Q0 |
Q2 |
Q1 |
Q0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
Step 3: Expand the present state-next state table to form the transition table.
Present State |
Next State |
Present inputs |
||||||
Q2 |
Q1 |
Q0 |
Q2 |
Q1 |
Q0 |
J2K2 |
J1K1 |
J0K0 |
0 |
0 |
0 |
0 |
0 |
1 |
0X |
0X |
1X |
0 |
0 |
1 |
0 |
1 |
0 |
0X |
1X |
X1 |
0 |
1 |
0 |
0 |
1 |
1 |
0X |
X0 |
1X |
0 |
1 |
1 |
1 |
0 |
0 |
1X |
X1 |
X1 |
1 |
0 |
0 |
1 |
0 |
1 |
X0 |
0X |
1X |
1 |
0 |
1 |
1 |
1 |
0 |
X0 |
1X |
X1 |
1 |
1 |
0 |
1 |
1 |
1 |
X0 |
X0 |
1X |
1 |
1 |
1 |
0 |
0 |
0 |
X1 |
X1 |
X1 |
‘X’ indicates a "don’t care" condition.
Step 4: Use Karnaugh maps to identify the present state logic functions for each of the inputs.
E.g. for J2 we get:
J2 = Q1Q0
Using similar techniques for the other inputs we get:
K2= Q1Q0
J1= Q0
K1= Q0
J0=1
K0=1
Step 5: Trace through indicates circuit should work correctly.
Step 6: Constructing Circuit
Figure 3-21 A three-bit synchronous counter
Like asynchronous counters, synchronous counters may be designed to meet a variety of specifications. For example, decade counters that count the binary sequence 0-9. In addition, we may implement bidirectional counters (i.e. they have the ability to count in ascending [0,1,2,3,4,5,6,7,8] and descending [8,7,6,5,4,3,2,1,0] order). In general, most bidirectional counters can be reversed at any point in their sequences e.g. 0,1,2,3,4,3,2,1,0,1,2,3,4. In this case there is an additional input which determines whether you want to count UP or DOWN.
Can you design Decade/Bidirectional synchronous counters?
How about a synchronous counter whose count sequence is not in numerical order?
Copyright © Adrian Als , 1999
This page was last modified: Wednesday, April 12, 2000
