Flip-flops are synchronous bistable storage devices capable of storing one bit. In this case synchronous means that the output state only changes at a specified point on a triggering input called the clock (C) That is, the output changes are synchronised with the clock signal.

The main difference between latches and flip-flops is the method used to change their states. Latches are level sensitive, or level-triggered. This means that the outputs are dependent on the voltage level applied, not on any signal transition. Flip-flops are edge-triggered, that is that they depend on the transition of a signal. This may either be a LOW-to-HIGH (rising edge) or a HIGH-to-LOW (falling edge) transition.

When using logic symbols, edge triggering is indicated by a small triangle inside the block at the clock-input (C). The absence or presence of a bubble, outside the block, is used to indicate rising and falling edge triggering, respectively. The logic symbols illustrating these concepts are shown in Figure 3-4.

Figure 3-4 Logic Symbols for D flip-flop (a) rising edge triggered (b) falling edge triggered

S-R Flip-Flop

The logic symbol for the S-R flip-flop is shown in Figure 3-5 and its operation outlined in Table 3-3.

Table 3-3 S-R Flip-flop Truth Table

Lets us now examine the output waveforms from the S-R flip-flop given the inputs shown in Figure 3-6. Assume that Q is HIGH initially.

Figure 3-6 Waveform diagram for S-R flip flop

The D Flip-Flop

The logic symbol for the D flip-flop is shown in Figure 3-7 and its operation outlined in Table 3-4. Notice that this flip-flop only has one input in addition to the clock called the D-input. Note that whatever is on the D-input when the trigger occurs is output at Q.

 Figure 3-7 Logic Symbols for D flip-flop (rising edge triggered)

Table 3-4 D Flip-flop Truth Table

J-K Flip-Flop

The J-K flip-flop is perhaps the most widely used type of flip-flop. Its function is identical to that of the S-R flip flop in the SET, RESET and HOLD conditions of operation. The difference is that the J-K flip-flop does not have any invalid states. The logic symbol for the J-K flip-flop is presented in Figure 3-8 and its corresponding truth table is listed in Table 3-5. Notice that for J=1 and K=1 the output toggles, that is to say that the output at time t is complemented at time t+1.

Figure 3-8 Logic Symbols for J-K flip-flop (rising edge triggered)

Table 3-3 J-K Flip-flop Truth Table

Let us now consider the J-K flip-flop operation as illustrated by the waveform diagrams in Figure 3-9. Again, we assume that Q is HIGH initially.

Figure 3-9 J-K waveform diagram

Flip Flops - with asynchronous inputs

Recall that the flip-flops discussed so far are called synchronous because the transfer of the data from the input to the output lines are synchronised with the triggering edge of the clock pulse. Most integrated circuit flip-flops also have asynchronous inputs that affect state of the flip-flop independent of the clock. These inputs are normally labeled preset (PRE) and clear (CLR) by the manufacturers. An active level on the preset will SET (1) the flip-flop, similarly an active level on the clear will RESET (0) the flip-flop. The logic symbol and the operation of a positive edge triggered J-K flip-flop with active LOW preset () and clear () inputs are shown in Figure 3-10 and Figure 3-11, respectively. Note that we assume that Q is HIGH initially

Figure 3-10 Logic Symbols for J-K flip-flop with and

Figure 3-11 J-K Flip-flop operation with preset and clear

Pulse-Triggered Master-Slave

The second class of flip-flop is the pulse-triggered or master-slave. These flip-flops are constructed from two separate flip-flops. The term pulse-triggered means that data are entered into the flip-flop on the leading edge of the clock pulse, but the output does not reflect the input state until the trailing edge of the clock pulse. This is due to the master flip-flop being rising edge triggered and the slave flip-flop being falling edge triggered as illustrated in Figure 3-12.

Figure 3-12 R-S Master-Slave configuration

Master-Slave J-K Flip-Flop

The logic symbol for the master-slave flip-flop only indicates the initial inputs to the master and the outputs from the slave as indicated by the J-K master-slave flip-flop shown in Figure 3-13.

Figure 3-13 Logic symbol for J-K master-slave flip-flop

Recall the truth table for the J-K flip-flop, shown below in Table 3-4.

Table 3-4 J-K Flip-flop Truth Table

 Let us now examine the operation of the master-slave J-K flip-flop as shown in Figure 3-14.

 Figure 3-14 Operation of master-slave J-k flip-flop

Copyright © Adrian Als , 1999
This page was last modified: Wednesday, April 12, 2000