A latch is a bistable multivibrator device that can store one bit (‘0’ or ‘1’) of data. Because of their storing capacity, latches are sometimes referred to as bistable memory devices. Latches may be used in groups of 4,8,16 or 32 to temporarily store a nibble, byte or word of data. They are also used often in microprocessor-based designs. Some texts make no distinction between latches and flip-flops. Note however that there is an essential difference in the ways they are triggered.
The S-R latch
The Set-Reset latch, commonly called S-R latch,
has two inputs (S and R), one true output (Q) and one complemented output (
) as shown in Figure 3-2. The crossing of the outputs is known
as cross coupling and this circuit is said to employ cross-coupled feed back. When the
output at Q is HIGH (1) the latch is said to be in the set state, similarly
when Q = 0 the latch is said to be in the clear (or Reset) state.
The logic symbol and the corresponding truth table for the S-R latch are presented in Figure 3-3 and Table 3-1 respectively.
Figure 3-3 Logic Symbol for S-R Latch
S |
R |
Q |
|
Operation |
0 |
0 |
|
|
Hold (no change) |
0 |
1 |
0 |
1 |
Reset |
1 |
0 |
1 |
0 |
Set |
1 |
1 |
? |
? |
Unstable |
Table 3-1 S-R Latch Truth Table
is the initial state of Q.
By introducing a time variable in the truth table, we may use the present input variable combinations and the latch state, at time t (Qt), to determine and next state of the latch at time t+1 (Qt+1). This type of table, referred to as the characteristic table, is illustrated in Table 3-2.
Present Input |
Present State |
Next State |
State Comment |
|
S |
R |
Qt |
Qt+1 |
|
0 |
0 |
0 |
0 |
Hold |
0 |
0 |
1 |
1 |
Hold |
0 |
1 |
0 |
0 |
Reset |
0 |
1 |
1 |
0 |
Reset |
1 |
0 |
0 |
1 |
Set |
1 |
0 |
1 |
1 |
Set |
1 |
1 |
0 |
Oscillating |
Invalid |
1 |
1 |
1 |
Oscillating |
Invalid |
Table 3-2 S-R Latch characteristic table
 | Note that the circuit designer is responsible for ensuring that S=1 and R=1 do not occur at the same time on the inputs of the S-R latch. |
| The S-R latch Circuit with active LOW inputs may be formed by replacing both of the NOR gates with NAND gates. |
| The Gated S-R latch has some additional circuitry and an enable (EN) input. This type of latch will not operate unless the enable is active. |
Can you identify of any applications where latches are employed?
Copyright © Adrian Als , 1999
This page was last modified: Wednesday, April 12, 2000
