A register that is capable of shifting data one bit at a time is called a shift register. The logical configuration of a serial shift register consists of a chain of flip-flops connected in cascade, with the output of one flip-flop being connected to the input of its neighbour. The operation of the shift register is synchronous; thus each flip-flop is connected to a common clock. Using D flip-flops forms the simplest type of shift-registers.
The basic data movements possible within a four-bit shift register is shown in Figure 3-22.
Figure 3-22 Data movement diagrams
Figure 3-23 shows the circuit diagram for a four-bit serial in-serial out shift register implemented using D flip-flops. Assuming that the register is initially clear, Figure 3-24 shown the waveform diagram when ‘1000’ is shifted through the register.
Figure 3-23 Four-bit serial in-serial out shift register
Figure 3-24 Waveform Diagram
 | Notice that although the inherent propagation delay is not included in the timing diagram it is still employed to achieve the correct results. |
Let us now take a closer look at the effect of shifting the binary digit ‘1’ through the register over time. Again, we assume that the register is initially reset and the bit enters the left-most stage.
At time t=0
0 |
0 |
0 |
0 |
(0) 10 |
At time t=1
1 |
0 |
0 |
0 |
(8) 10 |
At time t=2
0 |
1 |
0 |
0 |
(4) 10 |
At time t=3
0 |
0 |
1 |
0 |
(2) 10 |
At time t=4
0 |
0 |
0 |
1 |
(1) 10 |
At each time step from t=1 onwards, the right shift results in a state change which indicates a division by two operation. Similarly, if we operate in reverse chronological order (i.e. from t=4 to t=1), the left shift will result in a multiplication be two.
A bidirectional shift register, which is capable of shifting bits to the left (L) or right (R), will then be capable of performing modulo-2 division and multiplication operations. Figure 3-25 illustrates the logic circuit for the four-bit bidirectional shift register.
Figure 3-25 Four-bit serial bidirectional shift register
A HIGH on the
control input allows
data bits inside the register to be shifted to the right, and a LOW allows for the data to
be shifted to the left. Notice that when the input is
HIGH, G1 through G4 are enabled, and the state Q output from
each flip-flop is passed on to the D input of the following flip-flip. Consequently, on
each clock pulse the data is shifted one place to the right. Similarly, when that when the
is LOW, G5 through G8 are enabled,
and the state Q output from each flip-flop is passed on to the D input of the
preceding flip-flip. Now, on each clock pulse the data is shifted one place to the left.
Can the bidirectional shift register perform modulo-2 division operations that result in the remainder being non zero?
Copyright © Adrian Als , 1999
This page was last modified: Wednesday, April 12, 2000
