THE UNIVERSITY OF THE WEST INDIES

EXAMINATIONS OF DECEMBER 2004

Code and Name of Course: ELET2100 (EL21C) – MICROPROCESSORS I

Date and Time: Duration: 2 hours

INSTRUCTIONS TO CANDIDATES: This paper has 4 pages and 5 questions.

Answer any THREE (3) of FIVE (5) questions.

Question 1:

Explain the various hardware Interrupts available on the 8085 CPU. [10]

A Switch is connected to RST 5.5 of an 8085 CPU in a computer system. You wish the switch to trigger an emergency Siren controlled by Bit 0 of an output port 43H. Another switch connected to RST 6.5 of the same 8085 CPU will stop the Siren and pass control back to the original program. Explain and write commented Assembly Language code to handle the system described. State any assumptions made. [10]

Question 2:

Figure 1 shows the main Port address decoder for an 8085 CPU based computer. Determine the Port address ranges of the 3:8 Decoder. [6]

Explain, and show, how you would use this block decoder scheme, together with any

other logic gates and control signals, to design a block of four (4) output and four (4) input ports. [10]

Figure 1: Port address decoder

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The University of the West Indies Course Code: ELET2100

_______________________________________ _________________________________

DO NOT WRITE OR TYPE ON THE BACK OF THIS SHEET: USE ONE SIDE ONLY

INSTRUCTIONS: Each page must be signed by the FIRST AND SECOND EXAMINERS.

......................................... ............................................

First Examiner (P.Gibbs) Second Examiner (S.Mendes)

Date: 2004/11/09 Date: 2004/11/

Page 1

Question 3:

Figure 2 shows an asynchronous serial waveform of the ASCII character P using 8-data bits, one stop bit, and one parity bit. What is the Hex value of the character, the parity used, and the baud-rate (w = 5 ms)? [6]

Explain the operation of the software instructions on the 8085 CPU that are used for

serial communications. [6]

What are the limitations of this method of serial communication and explain how more modern systems are implemented? [8]

Figure 2: Waveform of the ASCII character ‘P’

Question 4:

A spare 8155 IC is inserted in your SDK-85 lab kit. Its CSR is port address 26H and the

256-byte memory begins at 2800H.

Choose a suitable input Timer frequency then program the Timer to generate a single pulse every 30s.

Use this pulse to trigger an RST 7.5 interrupt which then reads the eight (8) channels of

the A/D converter in Figure 3 and store them in memory from 2800H.

Explain how the complete system would work and show suitable commented code.

[20]

Figure 3: 8-channel A/D converter

PLEASE TURN OVER

The University of the West Indies Course Code: ELET2100

_________________________________________________ _______________________

DO NOT WRITE OR TYPE ON THE BACK OF THIS SHEET: USE ONE SIDE ONLY

INSTRUCTIONS: Each page must be signed by the FIRST AND SECOND EXAMINERS.

......................................... ...........................................

First Examiner (P.Gibbs) Second Examiner (S.Mendes)

Date: 2004/11/09 Date: 2004/11/

Page 2

Question 5:

( a ) Describe the Flags on the 8085 CPU. [5]

( b ) Indicate the contents of the Flags for the following instructions, assuming the

registers contain, before each instruction: A = 11H; BC = 1234H; DE = CDEFH;

HL = 1100H; and all Flags are cleared before the instruction is executed.

( i ) ANA D

( ii ) MVI B, 33H

( iii ) RAR

( iv ) ADD E

( v ) CMP H [10]

( c ) Use the same initial register data from ( b ) above, and the SP = 20C2H,

at the start of the program below, show the contents of the Stack area and

SP after each instruction:

PUSH D

PUSH H

PUSH B

POP D

What are the contents of the DE register pair? [5]

END OF QUESTION PAPER

The University of the West Indies Course Code: ELET2100

________________________________________________________________________

DO NOT WRITE OR TYPE ON THE BACK OF THIS SHEET: USE ONE SIDE ONLY

INSTRUCTIONS: Each page must be signed by the FIRST AND SECOND EXAMINERS.

......................................... ...........................................

First Examiner (P.Gibbs) Second Examiner (S.Mendes)

Date: 2004/11/09 Date: 2004/11/

Page 3